library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Automa_G is
PORT(
	X2: out Std_logic;
	X1: out Std_logic;
	X0: out Std_logic;
	prev_state: in std_logic_vector (2 downto 0)
);
end Automa_G;

architecture Behavioral of Automa_G is
	signal X2_INT: Std_logic:='0';
	signal X1_INT: Std_logic:='0';
	signal X0_INT: Std_logic:='0';
begin
	X2<=X2_INT;
	X1<=X1_INT;
	X0<=X0_INT;
	
	uscita_process: process(prev_state)
	begin
		case prev_state is
			when "000"=>
				X2_INT<='0';
				X1_INT<='0';
				X0_INT<='0';
			when "001"=>
				X2_INT<='0';
				X1_INT<='0';
				X0_INT<='1';
			when "010"=>
				X2_INT<='0';
				X1_INT<='1';
				X0_INT<='0';
			when "011"=>
				X2_INT<='0';
				X1_INT<='1';
				X0_INT<='1';
			when "100"=>
				X2_INT<='1';
				X1_INT<='0';
				X0_INT<='0';
			when others =>
				X2_INT<='0';
				X1_INT<='0';
				X0_INT<='0';
		end case;
	end process;
end Behavioral;
